Alliance

Complete set of free CAD tools and portable libraries for VLSI design. It includes a VHDL compiler and simulator, logic synthesis tools, and automatic place and route tools. Advanced verification tools for functional abstraction and static timing analysis are part of the system.

A complete set of portable CMOS libraries is provided, including a RAM generator, a ROM generator, and a data-path compiler.

Last updated 12 May, 2005


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License(s) :

GPLv2orlater

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About

Leadership
  • - Maintainer
Related Projects

Atlc, PCB, PythonCAD, QCad - Community Edition

Subprograms

asimut, bop, bbr, lvx, dpr, lynx, dreal, glop, druc, proof, fpgen, ring, fpmap, s2r, genlib, scmap, genpat, scr, genview, syf, graal, l2p

Versions

5.0-20050217

5.0-20050217 stable released 2005-02-17

User Community and Support

User manual available in HTML format from http://www-asim.lip6.fr/recherche/alliance/manual

General Resources
Support Resources

Development

Developer Resources
  • VCS Checkout Command: :pserver:anoncvs@asim.lip6.fr:/cvsroot
  • E-mail
Bug Tracking Resources
 

Please send comments on these web pages to bug-directory@fsf.org, send other questions to info@fsf.org.

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The copyright licensing notice below applies to this text. Any software described in this text has its own copyright notice and license, which can usually be found in the distribution itself.

Permission is granted to copy, distribute, and/or modify this document under the terms of the GNU Free Documentation License, Version 1.2 or any later version published by the Free Software Foundation; with no Invariant Sections, with no Front-Cover Texts, and with no Back-Cover Texts.