Icarus Verilog
This entry published by the Free Software Foundation.
Icarus Verilog
http://www.icarus.com/eda/verilog/
Icarus Verilog is a Verilog simulation and synthesis tool. It operates as a compiler, compiling source code writen in Verilog (IEEE-1364) into some target format. For batch simulation, the compiler can generate an intermediate form called vvp assembly. This intermediate form is executed by the ``vvp command. For synthesis, the compiler generates netlists in the desired format. The compiler proper is intended to parse and elaborate design descriptions written to the IEEE standard IEEE Std 1364-2001. The standard proper was released towards the middle of the year 2001, though in a rather pricey electronic form. This is a fairly large and complex standard, so it will take some time for it to get there, but that's the goal. NOTE: Under the Version information please browse the Installation link to find the proper download link.
Documentation
http://iverilog.wikia.com/wiki/Main_Page
Licensing
| License | Verified by | Verified on | Notes |
|---|---|---|---|
| GPLv2 | Kelly Hopkins | 2454846.515 January 2009 | |
| BSD 3Clause | Kelly Hopkins | 2454846.515 January 2009 | |
| Boost | Kelly Hopkins | 2454846.515 January 2009 |
Leaders and contributors
| Contact(s) | Role |
|---|---|
 Stephen Williams | Maintainer |
Resources and communication
| Audience | Resource type | URI |
|---|---|---|
| Developer | Download | ftp://ftp.icarus.com/pub/eda/verilog/v0.8/ |
| Developer | Homepage | http://www.icarus.com/eda/verilog/Release_Notes_for_Icarus_Verilog_0_8.html |
| Bug Tracking | Bug Tracking | http://www.icarus.com/eda/verilog/bugs.html |
Software prerequisites
Click here if you'd like to report a problem or make a suggestion that could
This entry (in part or in whole) was last reviewed on 15 January 2009.
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This page was last modified on 12 April 2011, at 15:04.