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Vtracer

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vtracer

http://sourceforge.net/projects/vtracer/
VCD is a standard signal trace format for HDL simulations. Often, users must compare behaviors of 2 different models which are supposed to work similarly. For example, when a Verilog core design is modified, users must verify that output pins of both the original and modified cores, behave the same if given the same stimulus. But the testbenches for each model are different, and therefore the behavors are slightly different also. The 'VTracer' package includes a set of configurable Perl scripts which performs comparison between pairs of signals from 2 different VCD files, and a sample Testbench demonstrating the integration of the tool.


Download

Download External-link-icon.png version 1.5 (stable)
released on 28 January 2005

VCS Checkout

:pserver:anonymous@cvs.sourceforge.net:/cvsroot/vtracer

Categories




Licensing

LicenseVerified byVerified onNotes
GPLv2Janet Casey17 June 2004



Leaders and contributors

Contact(s)Role
"Email DNaiger@bigfoot.com" Danny Naiger Maintainer


Resources and communication

Audience Resource type URI
Bug Tracking,Developer,Support E-mail mailto:DNaiger@bigfoot.com
Developer VCS Repository Webview http://sourceforge.net/cvs/?group_id=111719


Software prerequisites

This entry (in part or in whole) was last reviewed on 29 May 2010.



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Permission is granted to copy, distribute and/or modify this document under the terms of the GNU Free Documentation License, Version 1.3 or any later version published by the Free Software Foundation; with no Invariant Sections, no Front-Cover Texts, and no Back-Cover Texts. A copy of the license is included in the page “GNU Free Documentation License”.

The copyright and license notices on this page only apply to the text on this page. Any software or copyright-licenses or other similar notices described in this text has its own copyright notice and license, which can usually be found in the distribution or license text itself.


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