Verilog Testbench auxiliary tool
VCD is a standard signal trace format for HDL simulations. Often, users must compare behaviors of 2 different models which are supposed to work similarly. For example, when a Verilog core design is modified, users must verify that output pins of both the original and modified cores, behave the same if given the same stimulus. But the testbenches for each model are different, and therefore the behavors are slightly different also. The 'VTracer' package includes a set of configurable Perl scripts which performs comparison between pairs of signals from 2 different VCD files, and a sample Testbench demonstrating the integration of the tool.
released on 28 January 2005
|License||Verified by||Verified on||Notes|
|GPLv2||Janet Casey||17 June 2004|
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Resources and communication
|Developer||VCS Repository Webview||http://sourceforge.net/cvs/?group_id=111719|
This entry (in part or in whole) was last reviewed on 29 May 2010.