Difference between revisions of "Icarus Verilog"
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|Short description=a Verilog simulation and synthesis tool. | |Short description=a Verilog simulation and synthesis tool. | ||
|Full description=Icarus Verilog is a Verilog simulation and synthesis tool. It operates as a compiler, compiling source code writen in Verilog (IEEE-1364) into some target format. For batch simulation, the compiler can generate an intermediate form called vvp assembly. This intermediate form is executed by the ``vvp'' command. For synthesis, the compiler generates netlists in the desired format. The compiler proper is intended to parse and elaborate design descriptions written to the IEEE standard IEEE Std 1364-2001. The standard proper was released towards the middle of the year 2001, though in a rather pricey electronic form. This is a fairly large and complex standard, so it will take some time for it to get there, but that's the goal. '''NOTE: Under the Version information please browse the Installation link to find the proper download link.''' | |Full description=Icarus Verilog is a Verilog simulation and synthesis tool. It operates as a compiler, compiling source code writen in Verilog (IEEE-1364) into some target format. For batch simulation, the compiler can generate an intermediate form called vvp assembly. This intermediate form is executed by the ``vvp'' command. For synthesis, the compiler generates netlists in the desired format. The compiler proper is intended to parse and elaborate design descriptions written to the IEEE standard IEEE Std 1364-2001. The standard proper was released towards the middle of the year 2001, though in a rather pricey electronic form. This is a fairly large and complex standard, so it will take some time for it to get there, but that's the goal. '''NOTE: Under the Version information please browse the Installation link to find the proper download link.''' | ||
+ | |Homepage URL=http://iverilog.icarus.com/ | ||
|User level=intermediate | |User level=intermediate | ||
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|Computer languages=C,Verilog | |Computer languages=C,Verilog | ||
|Documentation note=http://iverilog.wikia.com/wiki/Main_Page | |Documentation note=http://iverilog.wikia.com/wiki/Main_Page | ||
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|Keywords=synthesizer,compiler,simulation,Verilog,compile,Semiconductor,synthesis,semiconductors,simulations,hardware description language,HDL | |Keywords=synthesizer,compiler,simulation,Verilog,compile,Semiconductor,synthesis,semiconductors,simulations,hardware description language,HDL | ||
− | | | + | |Version identifier=10.1.1 |
− | |Last review by= | + | |Version date=2016/02/10 |
− | |Last review date= | + | |Version status=stable |
+ | |Version download=ftp://icarus.com/pub/eda/verilog/v10/verilog-10.1.1.tar.gz | ||
+ | |Last review by=Alejandroindependiente | ||
+ | |Last review date=2017/02/26 | ||
|Submitted by=Database conversion | |Submitted by=Database conversion | ||
|Submitted date=2011-04-01 | |Submitted date=2011-04-01 | ||
− | | | + | |Status= |
− | | | + | |Is GNU=No |
− | | | + | |License verified date=2009-01-15 |
− | | | + | }} |
+ | {{Project license | ||
+ | |License=GPLv2 | ||
+ | |License verified by=Kelly Hopkins | ||
+ | |License verified date=2009-01-15 | ||
+ | }} | ||
+ | {{Project license | ||
+ | |License=BSD_3Clause | ||
+ | |License verified by=Kelly Hopkins | ||
+ | |License verified date=2009-01-15 | ||
+ | }} | ||
+ | {{Project license | ||
+ | |License=Boost | ||
+ | |License verified by=Kelly Hopkins | ||
|License verified date=2009-01-15 | |License verified date=2009-01-15 | ||
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}} | }} | ||
{{Person | {{Person | ||
+ | |Real name=Stephen Williams | ||
|Role=Maintainer | |Role=Maintainer | ||
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|Email=steve@icarus.com | |Email=steve@icarus.com | ||
|Resource URL= | |Resource URL= | ||
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|Interface=command-line | |Interface=command-line | ||
|Science=engineering | |Science=engineering | ||
− | |Software-development=compiler,small-specific-development-task | + | |Software-development=compiler, small-specific-development-task |
− | |Use=science,software-development | + | |Use=science, software-development |
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}} | }} | ||
+ | {{Featured}} |
Latest revision as of 16:21, 26 February 2017
Icarus Verilog
http://iverilog.icarus.com/
a Verilog simulation and synthesis tool.
Icarus Verilog is a Verilog simulation and synthesis tool. It operates as a compiler, compiling source code writen in Verilog (IEEE-1364) into some target format. For batch simulation, the compiler can generate an intermediate form called vvp assembly. This intermediate form is executed by the ``vvp command. For synthesis, the compiler generates netlists in the desired format. The compiler proper is intended to parse and elaborate design descriptions written to the IEEE standard IEEE Std 1364-2001. The standard proper was released towards the middle of the year 2001, though in a rather pricey electronic form. This is a fairly large and complex standard, so it will take some time for it to get there, but that's the goal. NOTE: Under the Version information please browse the Installation link to find the proper download link.
Licensing
License
Verified by
Verified on
Notes
Leaders and contributors
Contact(s) | Role |
---|---|
Stephen Williams | Maintainer |
Resources and communication
Audience | Resource type | URI |
---|---|---|
Developer | Download | ftp://ftp.icarus.com/pub/eda/verilog/v0.8/ |
Bug Tracking | Bug Tracking | http://www.icarus.com/eda/verilog/bugs.html |
Developer | Homepage | http://www.icarus.com/eda/verilog/Release_Notes_for_Icarus_Verilog_0_8.html |
Software prerequisites
Permission is granted to copy, distribute and/or modify this document under the terms of the GNU Free Documentation License, Version 1.3 or any later version published by the Free Software Foundation; with no Invariant Sections, no Front-Cover Texts, and no Back-Cover Texts. A copy of the license is included in the page “GNU Free Documentation License”.
The copyright and license notices on this page only apply to the text on this page. Any software or copyright-licenses or other similar notices described in this text has its own copyright notice and license, which can usually be found in the distribution or license text itself.