WikiSysop: Created page with "{{Entry |Name=Icarus Verilog |Short description=a Verilog simulation and synthesis tool. |Full description=Icarus Verilog is a Verilog simulation and synthesis tool. It operates ..."

2011-04-12T15:04:04Z

Created page with "{{Entry |Name=Icarus Verilog |Short description=a Verilog simulation and synthesis tool. |Full description=Icarus Verilog is a Verilog simulation and synthesis tool. It operates ..."

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{{Entry
|Name=Icarus Verilog
|Short description=a Verilog simulation and synthesis tool.
|Full description=Icarus Verilog is a Verilog simulation and synthesis tool. It operates as a compiler, compiling source code writen in Verilog (IEEE-1364) into some target format. For batch simulation, the compiler can generate an intermediate form called vvp assembly. This intermediate form is executed by the ``vvp'' command. For synthesis, the compiler generates netlists in the desired format. The compiler proper is intended to parse and elaborate design descriptions written to the IEEE standard IEEE Std 1364-2001. The standard proper was released towards the middle of the year 2001, though in a rather pricey electronic form. This is a fairly large and complex standard, so it will take some time for it to get there, but that's the goal. '''NOTE: Under the Version information please browse the Installation link to find the proper download link.'''
|User level=intermediate
|Status=Live
|Component programs=
|Homepage URL=http://www.icarus.com/eda/verilog/
|VCS checkout command=
|Computer languages=C,Verilog
|Documentation note=http://iverilog.wikia.com/wiki/Main_Page
|Paid support=
|IRC help=
|IRC general=
|IRC development=
|Related projects=
|Keywords=synthesizer,compiler,simulation,Verilog,compile,Semiconductor,synthesis,semiconductors,simulations,hardware description language,HDL
|Is GNU=n
|Last review by=Kelly Hopkins
|Last review date=2009-01-15
|Submitted by=Database conversion
|Submitted date=2011-04-01
|Version identifier=0.8.7
|Version date=2009-01-15
|Version status=stable
|Version download=http://iverilog.wikia.com/wiki/Installation_Guide
|License verified date=2009-01-15
|Version comment=
}}
{{Person
|Role=Maintainer
|Real name=Stephen Williams
|Email=steve@icarus.com
|Resource URL=
}}
{{Resource
|Resource audience=Developer
|Resource kind=Download
|Resource URL=ftp://ftp.icarus.com/pub/eda/verilog/v0.8/
}}
{{Resource
|Resource audience=Developer
|Resource kind=Homepage
|Resource URL=http://www.icarus.com/eda/verilog/Release_Notes_for_Icarus_Verilog_0_8.html
}}
{{Resource
|Resource audience=Bug Tracking
|Resource kind=Bug Tracking
|Resource URL=http://www.icarus.com/eda/verilog/bugs.html
}}
{{Software category
|Interface=command-line
|Science=engineering
|Software-development=compiler,small-specific-development-task
|Use=science,software-development
}}
{{Project license
|License=GPLv2
|License verified by=Kelly Hopkins
|License verified date=2009-01-15
}}
{{Project license
|License=BSD_3Clause
|License verified by=Kelly Hopkins
|License verified date=2009-01-15
}}
{{Project license
|License=Boost
|License verified by=Kelly Hopkins
|License verified date=2009-01-15
}}

Icarus Verilog - Revision history

WikiSysop: Created page with "{{Entry |Name=Icarus Verilog |Short description=a Verilog simulation and synthesis tool. |Full description=Icarus Verilog is a Verilog simulation and synthesis tool. It operates ..."