Difference between revisions of "Icarus Verilog"
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Revision as of 11:04, 12 April 2011
Icarus Verilog
http://iverilog.icarus.com/
a Verilog simulation and synthesis tool.
Icarus Verilog is a Verilog simulation and synthesis tool. It operates as a compiler, compiling source code writen in Verilog (IEEE-1364) into some target format. For batch simulation, the compiler can generate an intermediate form called vvp assembly. This intermediate form is executed by the ``vvp command. For synthesis, the compiler generates netlists in the desired format. The compiler proper is intended to parse and elaborate design descriptions written to the IEEE standard IEEE Std 1364-2001. The standard proper was released towards the middle of the year 2001, though in a rather pricey electronic form. This is a fairly large and complex standard, so it will take some time for it to get there, but that's the goal. NOTE: Under the Version information please browse the Installation link to find the proper download link.
Licensing
License
Verified by
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Notes
Leaders and contributors
| Contact(s) | Role |
|---|---|
| Stephen Williams | Maintainer |
Resources and communication
| Audience | Resource type | URI |
|---|---|---|
| Developer | Download | ftp://ftp.icarus.com/pub/eda/verilog/v0.8/ |
| Bug Tracking | Bug Tracking | http://www.icarus.com/eda/verilog/bugs.html |
| Developer | Homepage | http://www.icarus.com/eda/verilog/Release_Notes_for_Icarus_Verilog_0_8.html |
Software prerequisites
Permission is granted to copy, distribute and/or modify this document under the terms of the GNU Free Documentation License, Version 1.3 or any later version published by the Free Software Foundation; with no Invariant Sections, no Front-Cover Texts, and no Back-Cover Texts. A copy of the license is included in the page “GNU Free Documentation License”.
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