a Verilog simulation and synthesis tool.
Icarus Verilog is a Verilog simulation and synthesis tool. It operates as a compiler, compiling source code writen in Verilog (IEEE-1364) into some target format. For batch simulation, the compiler can generate an intermediate form called vvp assembly. This intermediate form is executed by the ``vvp command. For synthesis, the compiler generates netlists in the desired format. The compiler proper is intended to parse and elaborate design descriptions written to the IEEE standard IEEE Std 1364-2001. The standard proper was released towards the middle of the year 2001, though in a rather pricey electronic form. This is a fairly large and complex standard, so it will take some time for it to get there, but that's the goal. NOTE: Under the Version information please browse the Installation link to find the proper download link.
released on 10 February 2016
|License||Verified by||Verified on||Notes|
|License:GPLv2||Kelly Hopkins||15 January 2009|
|License:BSD 3Clause||Kelly Hopkins||15 January 2009|
|Boost||Kelly Hopkins||15 January 2009|
Leaders and contributors
Resources and communication
|Bug Tracking||Bug Tracking||http://www.icarus.com/eda/verilog/bugs.html|
This entry (in part or in whole) was last reviewed on 26 February 2017.
Permission is granted to copy, distribute and/or modify this document under the terms of the GNU Free Documentation License, Version 1.3 or any later version published by the Free Software Foundation; with no Invariant Sections, no Front-Cover Texts, and no Back-Cover Texts. A copy of the license is included in the page “GNU Free Documentation License”.
The copyright and license notices on this page only apply to the text on this page. Any software or copyright-licenses or other similar notices described in this text has its own copyright notice and license, which can usually be found in the distribution or license text itself.