Verilog
Verilog
http://iverilog.icarus.com
Icarus verilog compiler (transitional package)
Icarus Verilog is intended to compile all of the Verilog HDL as described in the IEEE-1364 standard. It is not quite there yet. It does currently handle a mix of structural and behavioral constructs.
The compiler can target either simulation, or netlist (EDIF).
This is a dummy transitional package that will ensure a proper upgrade path. This package may be safely removed after upgrading.
Licensing
License
Verified by
Verified on
Notes
License
Verified by
Debian: أحمد المحمودي (Ahmed El-Mahmoudy) <aelmahmoudy@sabily.org>
Verified on
24 August 2013
Notes
License: mit
License
Verified by
Debian: أحمد المحمودي (Ahmed El-Mahmoudy) <aelmahmoudy@sabily.org>
Verified on
24 August 2013
Notes
License: gpl-2+
Leaders and contributors
| Contact(s) | Role |
|---|---|
| Stephen Williams | contact |
Resources and communication
| Audience | Resource type | URI |
|---|---|---|
| Debian (Ref) | https://tracker.debian.org/pkg/verilog | |
| Debian (Ref) (R) | https://tracker.debian.org/pkg/iverilog | |
| Ruby (Ref) | https://rubygems.org/gems/verilog | |
| Download | http://iverilog.icarus.com |
Software prerequisites
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