Yosys
Yosys Open SYnthesis Suite
https://github.com/YosysHQ/yosys
This is a framework for RTL synthesis tools.
This is a framework for RTL synthesis tools. It currently has extensive Verilog-2005 support and provides a basic set of synthesis algorithms for various application domains.
Yosys can be adapted to perform any synthesis job by combining the existing passes (algorithms) using synthesis scripts and adding additional passes as needed by extending the yosys C++ code base.
Yosys is free software licensed under the ISC license (a GPL compatible license that is similar in terms to the MIT license or the 2-clause BSD license).
Third-party software distributed alongside this software is licensed under compatible licenses. Please refer to abc and libs subdirectories for their license terms.
Download
https://github.com/YosysHQ/yosys/archive/refs/tags/v0.50.tar.gz
VCS Checkout
git clone https://github.com/YosysHQ/yosys.git
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License
Verified by
tplaten, Mertgor
Verified on
14 February 2025
Leaders and contributors
Contact(s) | Role |
---|---|
Claire Xenia Wolf | Maintainer |
Resources and communication
Software prerequisites
Permission is granted to copy, distribute and/or modify this document under the terms of the GNU Free Documentation License, Version 1.3 or any later version published by the Free Software Foundation; with no Invariant Sections, no Front-Cover Texts, and no Back-Cover Texts. A copy of the license is included in the page “GNU Free Documentation License”.
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