Difference between revisions of "Alliance"
(Created page with "{{Entry |Name=Alliance |Short description=CAD tools |Full description=Complete set of free CAD tools and portable libraries for VLSI design. It includes a VHDL compiler and simul...") |
m (Text replacement - "|License=GPL-2.0-or-later" to "|License=GPLv2orlater") |
||
| (6 intermediate revisions by 4 users not shown) | |||
| Line 3: | Line 3: | ||
|Short description=CAD tools | |Short description=CAD tools | ||
|Full description=Complete set of free CAD tools and portable libraries for VLSI design. It includes a VHDL compiler and simulator, logic synthesis tools, and automatic place and route tools. Advanced verification tools for functional abstraction and static timing analysis are part of the system. A complete set of portable CMOS libraries is provided, including a RAM generator, a ROM generator, and a data-path compiler. | |Full description=Complete set of free CAD tools and portable libraries for VLSI design. It includes a VHDL compiler and simulator, logic synthesis tools, and automatic place and route tools. Advanced verification tools for functional abstraction and static timing analysis are part of the system. A complete set of portable CMOS libraries is provided, including a RAM generator, a ROM generator, and a data-path compiler. | ||
| + | |Homepage URL=https://www-soc.lip6.fr/equipe-cian/logiciels/alliance/ | ||
|User level=none | |User level=none | ||
| − | | | + | |Is High Priority Project=No |
|Component programs=asimut,bop,bbr,lvx,dpr,lynx,dreal,glop,druc,proof,fpgen,ring,fpmap,s2r,genlib,scmap,genpat,scr,genview,syf,graal,l2p | |Component programs=asimut,bop,bbr,lvx,dpr,lynx,dreal,glop,druc,proof,fpgen,ring,fpmap,s2r,genlib,scmap,genpat,scr,genview,syf,graal,l2p | ||
| − | |||
|VCS checkout command=:pserver:anoncvs@asim.lip6.fr:/cvsroot | |VCS checkout command=:pserver:anoncvs@asim.lip6.fr:/cvsroot | ||
|Computer languages=C | |Computer languages=C | ||
|Documentation note=User manual available in HTML format from http://www-asim.lip6.fr/recherche/alliance/manual | |Documentation note=User manual available in HTML format from http://www-asim.lip6.fr/recherche/alliance/manual | ||
| − | | | + | |Decommissioned/Obsolete=No |
| − | | | + | |Accepts cryptocurrency donations=No |
| − | |||
| − | |||
|Related projects=PythonCAD,Atlc,QCad_-_Community_Edition,PCB | |Related projects=PythonCAD,Atlc,QCad_-_Community_Edition,PCB | ||
|Keywords=CAD,vhdl,industrial design,alliance,desing and manufacturing | |Keywords=CAD,vhdl,industrial design,alliance,desing and manufacturing | ||
| − | | | + | |Version identifier=5.1.1 |
| − | |Last review by= | + | |Version date=2014/08/09 |
| − | |Last review date= | + | |Version status=stable |
| − | + | |Version download=http://www-asim.lip6.fr/pub/alliance/distribution/latest/alliance-5.1.1.tar.bz2 | |
| + | |Version comment=5.1.1 stable released 2014-08-09 | ||
| + | |Test entry=No | ||
| + | |Last review by=Bendikker | ||
| + | |Last review date=2018/04/16 | ||
|Submitted date=2011-04-01 | |Submitted date=2011-04-01 | ||
| − | | | + | |Is GNU=No |
| − | + | }} | |
| − | | | + | {{Project license |
| − | | | + | |License=GPLv2orlater |
| + | |License verified by=Janet Casey | ||
|License verified date=2001-02-17 | |License verified date=2001-02-17 | ||
| − | |||
}} | }} | ||
{{Person | {{Person | ||
|Role=Maintainer | |Role=Maintainer | ||
| − | | | + | }} |
| − | | | + | {{Resource |
| − | |Resource URL= | + | |Resource audience=Python (Ref) |
| + | |Resource URL=https://pypi.org/project/alliance | ||
| + | }} | ||
| + | {{Resource | ||
| + | |Resource audience=Ruby (Ref) | ||
| + | |Resource URL=https://rubygems.org/gems/alliance | ||
| + | }} | ||
| + | {{Resource | ||
| + | |Resource audience=Debian (Ref) | ||
| + | |Resource URL=https://tracker.debian.org/pkg/alliance | ||
}} | }} | ||
{{Resource | {{Resource | ||
| Line 40: | Line 51: | ||
}} | }} | ||
{{Software category | {{Software category | ||
| − | |Business=cad,productivity | + | |Business=cad, productivity |
| − | |Interface=library,x-window-system | + | |Interface=library, x-window-system |
|Works-with=cad | |Works-with=cad | ||
}} | }} | ||
| − | {{ | + | {{Featured}} |
| − | |||
| − | |||
| − | |||
| − | }} | ||
Latest revision as of 20:32, 16 August 2018
Alliance
https://www-soc.lip6.fr/equipe-cian/logiciels/alliance/
CAD tools
Complete set of free CAD tools and portable libraries for VLSI design. It includes a VHDL compiler and simulator, logic synthesis tools, and automatic place and route tools. Advanced verification tools for functional abstraction and static timing analysis are part of the system. A complete set of portable CMOS libraries is provided, including a RAM generator, a ROM generator, and a data-path compiler.
Licensing
License
Verified by
Verified on
Notes
Leaders and contributors
| Contact(s) | Role |
|---|---|
| Maintainer |
Resources and communication
| Audience | Resource type | URI |
|---|---|---|
| Bug Tracking,Developer,Support | mailto:alliance-users@asim.lip6.fr | |
| Python (Ref) | https://pypi.org/project/alliance | |
| Ruby (Ref) | https://rubygems.org/gems/alliance | |
| Debian (Ref) | https://tracker.debian.org/pkg/alliance |
Software prerequisites
Permission is granted to copy, distribute and/or modify this document under the terms of the GNU Free Documentation License, Version 1.3 or any later version published by the Free Software Foundation; with no Invariant Sections, no Front-Cover Texts, and no Back-Cover Texts. A copy of the license is included in the page “GNU Free Documentation License”.
The copyright and license notices on this page only apply to the text on this page. Any software or copyright-licenses or other similar notices described in this text has its own copyright notice and license, which can usually be found in the distribution or license text itself.