SIMSYNCH
SIMSYNCH
http://swiss.csail.mit.edu/~jaffer/SIMSYNCH
SIMSYNCH is a simulator for digital electronics at scales from chip to board.
The design files are comprised of Scheme definitions and expressions. These design files can be run as a Scheme program at high speed. The design files can also be translated into formats suitable for logic compilers (MACHXL, Verilog, and VHDL). SIMSYNCH simulates blocks of synchronous logic, signals whose states change simultaneously on a clock signal transition. Each block also has a reset signal, which forces all signals to the state specified in the design file. SIMSYNCH can simultaneously simulate multiple blocks with different clocks and resets. Devices can contain multiple blocks; Blocks can span multiple devices.
Licensing
License
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Notes
Leaders and contributors
| Contact(s) | Role |
|---|---|
| Aubrey Jaffer | Maintainer |
Resources and communication
| Audience | Resource type | URI |
|---|---|---|
| Developer | VCS Repository Webview | http://savannah.gnu.org/cgi-bin/viewcvs/synch/synch/ |
| Bug Tracking,Developer,Help,Support | mailto:agj@alum.mit.edu | |
| Help | Newsgroup | sci.electronics.cad |
Software prerequisites
| Kind | Description |
|---|---|
| Required to use | scm |
| Required to use | slib |
Permission is granted to copy, distribute and/or modify this document under the terms of the GNU Free Documentation License, Version 1.3 or any later version published by the Free Software Foundation; with no Invariant Sections, no Front-Cover Texts, and no Back-Cover Texts. A copy of the license is included in the page “GNU Free Documentation License”.
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