[[Business::cad]]

Oregano: 'Oregano' is an application for schematic capture and simulation of electrical circuits. The actual simulation is performed by SPICE, GNUcap or ngspice, but not necessary to run the application.

Profoil-WWW: This is a candidate for deletion: 1. Could not find any files/source code (website of author exists). PROFOIL-WWW is a Web version of PROFOIL - the author's low-speed airfoil design code. PROFOIL is not an all inclusive airfoil-design package. Inverse design, as later discussed, is its strength; analysis is not - it has none. The airfoil performance characteristics (viscous results) are determined with post-processing analysis tools (the Eppler code, Mark Drela's XFOIL, other codes, and finally when things look promising the wind tunnel). The Eppler code, XFOIL, the wind tunnel, etc must be separately obtained to complete the design-tool suite. If you develop a promising design, need some wind tunnel time and are associated with a potential sponsor, we might be able to help.

PythonCAD: The goal of the PythonCAD project is to create a fully scriptable drafting program that will match and eventually exceed features found in commercial CAD software. The program, currently under active development, is in its early stages but can do simple drawing.

QCad - Community Edition: QCad is a powerful but easy to use 2D CAD program for GNU/Linux. QCad uses DXF as its standard file format. You can load, merge and save DXF files. Furthermore it offers support for the HPGL format. While other CAD packages get complicated to use and unclear, QCad tries to stay comfortable and even an absolute beginner can create professional drawings with a minimum of effort.

Sc: The Edge Integration Station Controller (sc) is a program intrepreter for running applications that interface with and control Semiconductor Manufacturing equipment. It connects to equipment supporting GEM/SECS, HSMS, and serial protocols. Sc uses *NIX sockets and file sockets as its communication messaging bus.

Skidbladnir 2: Skidbladnir is a tool based on Altschuller's computer-aided inventing. He developed the 'ARIS' method, an algorithm for solving inventive tasks. The goal is to creata an ideal machine, taking into account both administrative and technical considerations.

Speckle: Speckle is an open source cloud-based data platform for AEC. It provides a method of liberating data from one platform to another in a quick, manageable, and efficient way. For example it can be used to move geometry and data from the proprietary Autodesk Revit over to the libre Blender project.

TkGate: 'TkGate' is an event-driven digital circuit simulator with a TCL/Tk-based graphical editor. It supports a wide range of primitive circuit elements and user-defined modules for hierarchical design. TkGate has multi-lingual support for English, Japanese, French, German, Spanish, Welsh, and Catalan.

Umbrello UML Modeller: Umbrello UML Modeller is a Unified Modelling Language diagram tool for KDE. It is able to produce Class diagrams, Sequence diagrams, Collaboration diagrams, Use Case diagrams, Activity diagrams, and State diagrams. It uses an XMI-based file format. It is now part of KDE and will be released with KDE 3.2

Varkon: VARKON can be used as a traditional CAD-system with drafting, modelling and visualization if you want to but the real power of VARKON is in parametric modelling and CAD applications development. VARKON includes interactive parametric modelling in 2D or 3D but also the unique MBS programming language integrated in the graphical environment.

ViPEC: VIPEC is an network analyser for electrical networks. It takes a description of an electrical network, and performs a simulation of the circuit response in the frequency domain. Output is in the form of 2-port parameters, and can be plotted on a grid and in Smithchart format. VIPEC supports various lumped circuit elements, as well as elements like transmission lines and 2-port data files.

Vtracer: VCD is a standard signal trace format for HDL simulations. Often, users must compare behaviors of 2 different models which are supposed to work similarly. For example, when a Verilog core design is modified, users must verify that output pins of both the original and modified cores, behave the same if given the same stimulus. But the testbenches for each model are different, and therefore the behavors are slightly different also. The 'VTracer' package includes a set of configurable Perl scripts which performs comparison between pairs of signals from 2 different VCD files, and a sample Testbench demonstrating the integration of the tool.

Xi: The aim of this project is to provide a common infrastructure for free CAD software—basically, a GUI ready to fill with domain-specific code. It covers common, reusable features such as an undo/redo mechanism, property editor, library browser, navigation between files and management of file dependencies. The domain modules (which are intended to be written in a scripting language as far as reasonably possible) provide a description of the actual objects and operations. This architecture roughly compares to that of Emacs. Xi is still in early development.

Free Software Foundation!