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- ViPEC
- VIPEC is an network analyser for electrical networks. It takes a description of an electrical network, and performs a simulation of the circuit response in the frequency domain. Output is in the form of 2-port parameters, and can be plotted on a grid and in Smithchart format. VIPEC supports various lumped circuit elements, as well as elements like transmission lines and 2-port data files.
- Vtracer
- VCD is a standard signal trace format for HDL simulations. Often, users must compare behaviors of 2 different models which are supposed to work similarly. For example, when a Verilog core design is modified, users must verify that output pins of both the original and modified cores, behave the same if given the same stimulus. But the testbenches for each model are different, and therefore the behavors are slightly different also. The 'VTracer' package includes a set of configurable Perl scripts which performs comparison between pairs of signals from 2 different VCD files, and a sample Testbench demonstrating the integration of the tool.
- Xi
- The aim of this project is to provide a common infrastructure for free CAD software—basically, a GUI ready to fill with domain-specific code. It covers common, reusable features such as an undo/redo mechanism, property editor, library browser, navigation between files and management of file dependencies. The domain modules (which are intended to be written in a scripting language as far as reasonably possible) provide a description of the actual objects and operations. This architecture roughly compares to that of Emacs. Xi is still in early development.
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