From Free Software Directory
Jump to: navigation, search



Verilog Testbench auxiliary tool

VCD is a standard signal trace format for HDL simulations. Often, users must compare behaviors of 2 different models which are supposed to work similarly. For example, when a Verilog core design is modified, users must verify that output pins of both the original and modified cores, behave the same if given the same stimulus. But the testbenches for each model are different, and therefore the behavors are slightly different also. The 'VTracer' package includes a set of configurable Perl scripts which performs comparison between pairs of signals from 2 different VCD files, and a sample Testbench demonstrating the integration of the tool.



Verified by

Verified on




Verified by

Janet Casey

Verified on

17 June 2004

Leaders and contributors

Danny Naiger Maintainer

Resources and communication

AudienceResource typeURI
DeveloperVCS Repository Webviewhttp://sourceforge.net/cvs/?group_id=111719
Bug Tracking,Developer,SupportE-mailmailto:DNaiger@bigfoot.com

Software prerequisites


Permission is granted to copy, distribute and/or modify this document under the terms of the GNU Free Documentation License, Version 1.3 or any later version published by the Free Software Foundation; with no Invariant Sections, no Front-Cover Texts, and no Back-Cover Texts. A copy of the license is included in the page “GNU Free Documentation License”.

The copyright and license notices on this page only apply to the text on this page. Any software or copyright-licenses or other similar notices described in this text has its own copyright notice and license, which can usually be found in the distribution or license text itself.