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The design files are comprised of Scheme definitions and expressions. These design files can be run as a Scheme program at high speed. The design files can also be translated into formats suitable for logic compilers (MACHXL, Verilog, and VHDL). SIMSYNCH simulates blocks of synchronous logic, signals whose states change simultaneously on a clock signal transition. Each block also has a reset signal, which forces all signals to the state specified in the design file. SIMSYNCH can simultaneously simulate multiple blocks with different clocks and resets. Devices can contain multiple blocks; Blocks can span multiple devices.


LicenseVerified byVerified onNotes
GPLv2orlaterTed Teah27 February 2006

Leaders and contributors

Aubrey Jaffer Maintainer

Resources and communication

Audience Resource type URI
Developer VCS Repository Webview
Bug Tracking,Developer,Help,Support E-mail
Help Newsgroup sci.electronics.cad

Software prerequisites

Kind Description
Required to use slib
Required to use scm

This entry (in part or in whole) was last reviewed on 27 February 2006.


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