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SIMSYNCH

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SIMSYNCH

http://swiss.csail.mit.edu/~jaffer/SIMSYNCH
The design files are comprised of Scheme definitions and expressions. These design files can be run as a Scheme program at high speed. The design files can also be translated into formats suitable for logic compilers (MACHXL, Verilog, and VHDL). SIMSYNCH simulates blocks of synchronous logic, signals whose states change simultaneously on a clock signal transition. Each block also has a reset signal, which forces all signals to the state specified in the design file. SIMSYNCH can simultaneously simulate multiple blocks with different clocks and resets. Devices can contain multiple blocks; Blocks can span multiple devices.


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Download External-link-icon.png version NO_VERSION_DATA (stable)
released on 1 January 1970

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Licensing

LicenseVerified byVerified onNotes
GPLv2orlaterTed Teah27 February 2006



Leaders and contributors

Contact(s)Role
"Email agj@alum.mit.edu" Aubrey Jaffer Maintainer


Resources and communication

Audience Resource type URI
Developer VCS Repository Webview http://savannah.gnu.org/cgi-bin/viewcvs/synch/synch/
Bug Tracking,Developer,Help,Support E-mail mailto:agj@alum.mit.edu
Help Newsgroup sci.electronics.cad


Software prerequisites

Kind Description
Required to use scm
Required to use slib

This entry (in part or in whole) was last reviewed on 27 February 2006.



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Permission is granted to copy, distribute and/or modify this document under the terms of the GNU Free Documentation License, Version 1.3 or any later version published by the Free Software Foundation; with no Invariant Sections, no Front-Cover Texts, and no Back-Cover Texts. A copy of the license is included in the page “GNU Free Documentation License”.

The copyright and license notices on this page only apply to the text on this page. Any software or copyright-licenses or other similar notices described in this text has its own copyright notice and license, which can usually be found in the distribution or license text itself.


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