The design files are comprised of Scheme definitions and expressions. These design files can be run as a Scheme program at high speed. The design files can also be translated into formats suitable for logic compilers (MACHXL, Verilog, and VHDL). SIMSYNCH simulates blocks of synchronous logic, signals whose states change simultaneously on a clock signal transition. Each block also has a reset signal, which forces all signals to the state specified in the design file. SIMSYNCH can simultaneously simulate multiple blocks with different clocks and resets. Devices can contain multiple blocks; Blocks can span multiple devices.
released on 30 June 2010
|License||Verified by||Verified on||Notes|
|GPLv2orlater||Ted Teah||27 February 2006|
Leaders and contributors
Resources and communication
|Developer||VCS Repository Webview||http://savannah.gnu.org/cgi-bin/viewcvs/synch/synch/|
|Required to use||scm|
|Required to use||slib|
This entry (in part or in whole) was last reviewed on 14 February 2017.
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