Complete set of free CAD tools and portable libraries for VLSI design. It includes a VHDL compiler and simulator, logic synthesis tools, and automatic place and route tools. Advanced verification tools for functional abstraction and static timing analysis are part of the system. A complete set of portable CMOS libraries is provided, including a RAM generator, a ROM generator, and a data-path compiler.
DocumentationUser manual available in HTML format from http://www-asim.lip6.fr/recherche/alliance/manual
released on 9 August 2014
|License||Verified by||Verified on||Notes|
|GPLv2orlater||Janet Casey||17 February 2001|
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This entry (in part or in whole) was last reviewed on 24 December 2016.
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